VHDL Generation Tool for a Highly parallel implementation of a CNN on FPGA

In this project we present a software tool designed and implemented in Java to generate VHDL code for Convolution-->Pooling-->Fully connected style of deep convolutional neural networks (CNN). The implementation represents a a hardware accelerator on an FPGA platform. The hardware accelerator and generation tool have the following features:

1. VHDL generator with the following features:
   • Easy configuration, support for externally pre-configured models, and support for model checking and validation
   • Flexibility, scalability, and adaptability with small and large-scale CNN models
   • With Standard HLS tools such as Vivado HLS, users have to go through the lengthy development process by programing in a high-level language. By contrast, in our tool users only have to configure the model of their choice without doing any programming.
2. Scalable, reconfigurable, fully-pipelined, and massively parallel accelerator
3. Tested the VHDL generator on two benchmarked models (LeNet and AlexNet) and other hand-tuned models. The system can process up to 125K Images/s for LeNet and achieved peak performance of 611.52 GOP/s for AlexNet

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Technologies Used: Java, Vivado, ModelSim, VHDL, FPGA.